Regviz

Silicon Labs /EFR32BG22C222F352GM40 /MODEM_S /ANTSWCTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ANTSWCTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C112F352GM32/MODEM_NS/ANTSWCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ANTDFLTSEL0ANTCOUNT0 (US_2)ANTSWTYPE 0 (ANTSWRST)ANTSWRST 0 (CFGANTPATTEN)CFGANTPATTEN 0 (ANTSWENABLE)ANTSWENABLE 0EXTDSTOPPULSECNT

ANTSWTYPE=US_2

Description

No Description

Fields

ANTDFLTSEL

Ant Default Select
ANTCOUNT

Total Ant count
ANTSWTYPE

Ant Switch Type

0 (US_2): 2us ant switching

1 (US_4): 4us ant switching

2 (US_6): 6us ant switching

3 (US_8): 8us ant switching
ANTSWRST

Ant SW rst pulse
CFGANTPATTEN

Configure Ant Pattern Enable
ANTSWENABLE

Ant sw enable
EXTDSTOPPULSECNT

Extend Stop Pulse Counter

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data